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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco

May 22, 2026

IND-PUNE, IndiaOnsiteFull-timeEngineeringLead

Skills & Technologies

PythonSOC

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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune) at Cisco | Hiring.Camp